
module OutputMemory(
  input  wire       clk,
  input  wire       rst_n,
  input  wire [4:0] addr,
  input  wire       wr,
  input  wire [9:0] wdata,
  output reg  [9:0] rdata,
  input  wire [4:0] addr2,
  output reg  [9:0] rdata2
);

reg [9:0] data_array_00;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_00 <= #1 10'b0;
    else if(wr && (addr==5'd0))
        data_array_00 <= #1 wdata;
end

reg [9:0] data_array_01;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_01 <= #1 10'b0;
    else if(wr && (addr==5'd1))
        data_array_01 <= #1 wdata;
end

reg [9:0] data_array_02;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_02 <= #1 10'b0;
    else if(wr && (addr==5'd2))
        data_array_02 <= #1 wdata;
end

reg [9:0] data_array_03;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_03 <= #1 10'b0;
    else if(wr && (addr==5'd3))
        data_array_03 <= #1 wdata;
end

reg [9:0] data_array_04;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_04 <= #1 10'b0;
    else if(wr && (addr==5'd4))
        data_array_04 <= #1 wdata;
end

reg [9:0] data_array_05;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_05 <= #1 10'b0;
    else if(wr && (addr==5'd5))
        data_array_05 <= #1 wdata;
end

reg [9:0] data_array_06;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_06 <= #1 10'b0;
    else if(wr && (addr==5'd6))
        data_array_06 <= #1 wdata;
end

reg [9:0] data_array_07;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_07 <= #1 10'b0;
    else if(wr && (addr==5'd7))
        data_array_07 <= #1 wdata;
end

reg [9:0] data_array_08;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_08 <= #1 10'b0;
    else if(wr && (addr==5'd8))
        data_array_08 <= #1 wdata;
end

reg [9:0] data_array_09;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_09 <= #1 10'b0;
    else if(wr && (addr==5'd9))
        data_array_09 <= #1 wdata;
end

reg [9:0] data_array_10;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_10 <= #1 10'b0;
    else if(wr && (addr==5'd10))
        data_array_10 <= #1 wdata;
end

reg [9:0] data_array_11;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_11 <= #1 10'b0;
    else if(wr && (addr==5'd11))
        data_array_11 <= #1 wdata;
end

reg [9:0] data_array_12;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_12 <= #1 10'b0;
    else if(wr && (addr==5'd12))
        data_array_12 <= #1 wdata;
end

reg [9:0] data_array_13;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_13 <= #1 10'b0;
    else if(wr && (addr==5'd13))
        data_array_13 <= #1 wdata;
end

reg [9:0] data_array_14;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_14 <= #1 10'b0;
    else if(wr && (addr==5'd14))
        data_array_14 <= #1 wdata;
end

reg [9:0] data_array_15;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_15 <= #1 10'b0;
    else if(wr && (addr==5'd15))
        data_array_15 <= #1 wdata;
end

reg [9:0] data_array_16;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_16 <= #1 10'b0;
    else if(wr && (addr==5'd16))
        data_array_16 <= #1 wdata;
end

reg [9:0] data_array_17;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_array_17 <= #1 10'b0;
    else if(wr && (addr==5'd17))
        data_array_17 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        rdata <= #1 10'b0;
    else
        case(addr)
        5'd00  : rdata <= #1 data_array_00;
        5'd01  : rdata <= #1 data_array_01;
        5'd02  : rdata <= #1 data_array_02;
        5'd03  : rdata <= #1 data_array_03;
        5'd04  : rdata <= #1 data_array_04;
        5'd05  : rdata <= #1 data_array_05;
        5'd06  : rdata <= #1 data_array_06;
        5'd07  : rdata <= #1 data_array_07;
        5'd08  : rdata <= #1 data_array_08;
        5'd09  : rdata <= #1 data_array_09;
        5'd10  : rdata <= #1 data_array_10;
        5'd11  : rdata <= #1 data_array_11;
        5'd12  : rdata <= #1 data_array_12;
        5'd13  : rdata <= #1 data_array_13;
        5'd14  : rdata <= #1 data_array_14;
        5'd15  : rdata <= #1 data_array_15;
        5'd16  : rdata <= #1 data_array_16;
        5'd17  : rdata <= #1 data_array_17;
        default: rdata <= #1 10'b0;
        endcase
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        rdata2 <= #1 10'b0;
    else
        case(addr2)
        5'd00  : rdata2 <= #1 data_array_00;
        5'd01  : rdata2 <= #1 data_array_01;
        5'd02  : rdata2 <= #1 data_array_02;
        5'd03  : rdata2 <= #1 data_array_03;
        5'd04  : rdata2 <= #1 data_array_04;
        5'd05  : rdata2 <= #1 data_array_05;
        5'd06  : rdata2 <= #1 data_array_06;
        5'd07  : rdata2 <= #1 data_array_07;
        5'd08  : rdata2 <= #1 data_array_08;
        5'd09  : rdata2 <= #1 data_array_09;
        5'd10  : rdata2 <= #1 data_array_10;
        5'd11  : rdata2 <= #1 data_array_11;
        5'd12  : rdata2 <= #1 data_array_12;
        5'd13  : rdata2 <= #1 data_array_13;
        5'd14  : rdata2 <= #1 data_array_14;
        5'd15  : rdata2 <= #1 data_array_15;
        5'd16  : rdata2 <= #1 data_array_16;
        5'd17  : rdata2 <= #1 data_array_17;
        default: rdata2 <= #1 10'b0;
        endcase
end

endmodule
